About the role
We are seeking an experienced Principal Engineer, VLSI Design Engineering to lead verification efforts for complex IP blocks and fullchip designs. In this role, you will drive functional verification closure, mentor engineering teams, and collaborate across multiple disciplines to ensure design quality and silicon success.
Key Responsibilities:
Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs
Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks
Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards
Drive functional coverage-driven verification closure and ensure comprehensive design validation including Functional Coverage planning, development, debug and closure
Develop and maintain System Verilog Assertions (SVA) for design verification, including coding, porting, and maintenance activities
Collaborate with design architects, RTL designers, and post-silicon validation teams to ensure seamless verification integration
Create and optimize verification automation tools and scripts to enhance design and verification productivity
Investigate, debug, and perform root-cause analysis of design failures through cross-functional team collaboration
Mentor junior engineers and contribute to the continuous improvement of verification methodologies and best practices
Required Qualifications:
7 to 11 years of relevant experience in VLSI design verification
Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering; Master's degree preferred
Advanced proficiency in C, Verilog, SystemVerilog, and UVM (Universal Verification Methodology)
Hands-on experience with industry-standard verification tools including Xcellium, Verdi, and JasperGold formal verification tools
Demonstrated expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off
Proven ability to lead technical projects and manage stakeholder relationships effectively
Bring in AI/ML/Automation based initiatives
Excellent written and verbal communication skills with demonstrated ability to adapt to dynamic project requirements and deliver results under challenging schedules
Preferred Qualifications:
Experience with NAND flash memory protocols and memory design verification
Track record of mentoring junior engineers and contributing to process improvements
Experience with formal verification methodologies and assertion-based verification
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various pers